A 12-bit 5MS/s Synchronous SAR ADC With Comparator Using High Gain Pre-amplifier

초록

This paper proposes a design technique to address the challenges of using a 1V analog supply to achieve low-power operation in a SAR ADC circuit. Specifically, we focus on the design of the comparator circuit, which can be difficult due to reduced decision accuracy caused by noise and other factors. To overcome this issue, we suggest maximizing the gain of the pre-amplifier in the comparator circuit, which can improve decision accuracy and overall performance of the circuit. Importantly, this approach allows for less emphasis on the bandwidth of the circuit, making it more suitable for low-power applications. Simulation studies demonstrate the effectiveness of the proposed design technique in achieving high accuracy while maintaining low power consumption. This approach provides a valuable contribution to the field of analog circuit design for low-power SAR ADC applications.

키워드